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78P2352-DB stm1e/e4/oc3 demo board demo board manual 1 august 2005 introduction this manual will explain the design and operation of the 78P2352-DB demo board (board rev. d2352t8 c ). the 78p2352 is teridians latest dual channel line interface unit (liu) for 155mbit/s sonet/sdh (oc-3 or stm-1e) and 140mbit/s pdh (e4) applications. description the 78P2352-DB demo board is designed to facilitate easy evaluation of the 78p2352 line interface unit (liu) in the electrical (coaxial) domain. the board can be easily configured into different operating modes with the on board configuration headers and dipswitches. on the line side, all the necessary discrete components are included for transmitting and receiving cmi signal on the 75 ? coaxial line. if needed, all other discrete components can be populated to support the optical line interface. features ? allows easy evaluation of the 78p2352 ? includes configuration headers and dipswitches for hw control options ? link status leds for both channels ? options for using on-boa rd crystal oscillator or external reference clock ? 17.408mhz and 19.44mhz on-board crystal oscillators allow easy evaluations of pdh and sdn/sonet applications. ? 48-pin box connector for parallel (nibble) interface ? sma connectors for seri al (lvpecl) interface ? 3.3v power supply ordering info part description order number 78p2352-igt demo board 78P2352-DB 78p2352 transformers & protection diodes bnc bncbnc bnc 48-pin connector: parallel (nibble) interface sma connectors: channel 1 serial interface sma connectors: channel 2 serial interface configuration switch s1 configuration switch sw2 frst lpbk2 lpbk1 ckmode txout0 txout1 cksl rcsl txpd configuration switch sw1 monitor cmi/ecl parallel/serial e4/stm1/sts3 sma ext. clock optics module optics module + o _ figure 1: d2352t8 c board block diagram downloaded from: http:///
78P2352-DB demo board manual 2 required equipment ? teridian d2352t8 c demo board ? power supply, 3.3v, 1.5amp ? banana plug connection cable for power supply ? 75 ? coax cable set. ? test equipment (signal source generator, jitter measurement, etc.) getting started 1. configurations for the headers : a) jp1 : shunt connects to p/s to use sw1 b) jp2 : shunt connects to e/s to use sw1 c) jp3 : shunt connects to gnd to use hardware control mode d) jp4 : shunt connects to mon to use sw1 e) jp5 : shunt connects to c/e to use sw1 f) jp6 : connect shunt to e4 to use 19.44m xo for stm-1/sts-3 mode or connect to stm1 to use 17.408m xo for e4 mode g) jp7 : connect shunt to loc to use on-board crystal oscillators for reference clock or connect to ext to use external clock source provided at (ckref) sma connector 2. configurations for the dipswitches: typical settings in bold sw1 pin 1: line interface select - cmi or ecl - see sen_cmi pin description in datasheet pin 2: receiver monitor mode - enabled or disabled - see sck_mon pin description in datasheet pin 3: system interface select - parallel or serial - see sdi_par pin description in datasheet pin 4: rate select - e4 or smt1/sts3 - see sdo_e4 pin description in datasheet sw2 pin 1: transmitter power down - enabled or disabled - see txpd pin description in datasheet pin 2: redundant channel - enabled or disabled - not used in 78p2352 s1 pin 1: fifo phase initialization - float (normal operation) - see frst pin description in datasheet pin 2: channel 2 loopback - float (remote loopback) - see lpbk2 pin description in datasheet pin 3: channel 1 loopback - float (remote loopback) - see lpbk1 pin description in datasheet pin 4: clock (timing) mode select - high (plesiochronous mode) - see ckmode pin description in datasheet pin 5: cmi tx amplitude boost - low (normal) - see txout0 pin description in datasheet pin 6: cmi tx peaking control - float (no peaking) - see txout1 pin description in datasheet pin 7: reference clock frequency - low (17.408mhz or 19.44mhz) - see cksl pin description in datasheet pin 8: unused frst lpbk2 lpbk1 ckmode txout0 txout1 cksl + o _ n/c typical s1 settings 3. apply 3.3v power to the demo board downloaded from: http:///
78P2352-DB demo board manual 3 demo board description configuring bit rate the d2352t8 c can be configured for either e4 or sts3/stm1 rates by sw1 (pin 4). a corresponding reference clock input is required for operation. the compatible reference clocks for each rate are as follows: rate reference clock e4 17.408mhz, 139.264 mhz sts3 /stm1 19.44mhz, 77.76mhz, 155.52 mhz s1 (pin 7) is used to configure the reference clock frequency based on the selected bit rate. cksl reference clock high 139.264 mhz, 155.52 mhz float 77.76mhz low 17.408mhz, 19.44mhz the 78P2352-DB provides on-board 17.408mhz and 19.44mhz crystal oscillators as well as an sma connector for use of external reference clock sources. headers jp6 and jp7 allow easy selection of the reference clock source. note : if using any system/timing interface other than the recommended serial plesiochronous mode, an external reference clock source must be provided at the sma input labeled ckref and must be synchronous to the transmit data (and timing) source. line interface the 78P2352-DB is pre-configured and shipped to allow easy evaluation of the cmi encoded, coaxial line interface. footprints for optics modules, however, are provided for evaluating the optical line interface of the 78p2352. for more information on configuring the d2352t8 c board in optical (nrz) mode, please contact teridians applications support group. transmit signal path the transmitters coaxial connectors are connected to the liu transmitter pins (cmxp, cmxn) through a 1:1ct (center-tapped) transformer. the transformer center tap is tied to vcc to bias the transmitter drivers. the signal path is differentially terminated with a 75 ? resistor on the liu side of the transformer. the termination resistor, in combination with the characteristic impedance of the transformer and the line impedance create the required pulse shaping impedance for the lius driver. the user may configure serial or parallel interface by changing sw1 (pin 3), although serial plesiochronous mode is recommended to eliminate the need for a synchronous timing relationship between the transmit clock/data and the reference clock. when the parallel (system) interface is chosen, the 48-pin box connector u2 can be used to connect other digital control boards. by default the liu expects transmit data to clock in on the rising clock edge so the transmitter source (i.e framer) should clock out transmit data on the clocks falling edge. if using this interface, the user must ensure the reference clock is synchronous with the tran smit clock/data source. sma connectors support the option for a serial (system) interface. each channel provides four sma connectors, two for the differential clock (sixckp/n) and two for the respective differential data signal (sixdp/n). these inputs accept lvpecl differential signals, which are ac-coupled and differentially terminated with 100 ? at the liu. if using any serial timing mode other than plesiochronous mode, the user must ensure the reference clock is synchronous with the transmit clock/data source. downloaded from: http:///
78P2352-DB demo board manual 4 receive signal path the line side (coax) receiver interface has the same architecture as the transmit interface, except the transformer windings center tap is left open. the received signal is internally equalized for dispersive cable attenuation and decoded in the cmi to nrz decoder. the user may configure serial or parallel interface by changing sw1 (pin 3), although serial plesiochronous mode is recommended. if selecting the parallel interface, data to the system (i.e. framer) passes through the 48-pin box connector. the receive data is clocked out at the falling edge of the receive clock. this is the default state of the liu. sma connectors support the option for a serial (system) interface. each channels serial interface provides four sma connectors, two for the differential clock (soxckp/n) and two for the respective differential data signal (soxdp/n). these outputs provide lvpecl differential signals, which are ac-coupled to the system at the sma connectors. supplemental surge protection optional surge protection circuitry is included on the coax line side to ensure proper operation of the device during the presence of differential voltage surges, as called for by itu-t, bellcore, and iec specifications. protection diode u3 provides additional protection against esd and power supply transients at the power supply banana jacks. consult the application note for more information on supplemental surge protection for electrical interfaces. loopback operation s1 (pins 2 and 3) also provides controls for configuring the internal loopback modes. when the pin is pulled low , the chip is in the normal mode. when the pin is pulled high , the receiver uses the transmitter output signal as its input, known as local (analog) loopback. when the pin is floating , the received signal is looped back to the transmitter, known as remote (digital) loopback. differential test points the following test points are provided to facilitate test and measurement. test point signal description pdt1 pdt2 pwr power plane test points pdt3 si2ckp/n channel 2 transmit serial clock / data input pdt4 si2dp/n pdt5 so2ckp/n channel 2 receive serial clock / data output pdt6 so2dp/n pdt7 si1ckp/n channel 1 transmit serial clock / data input pdt8 si1dp/n pdt9 so1ckp/n channel 1 receive serial clock / data output pdt10 so1dp/n pdt13 pdt16 rxxp/n receive serial cmi or lvpecl input pdt14 pdt17 cmixp/n transmit serial cmi data output pdt15 pdt17 eclxp/n transmit serial (nrz) lvpecl data output status pins the 78p2352 provides both open drain and cmos versions for the status pins. on the demo board, resistor population options are available to evaluate different version of chips. the demo boards are populated by open drain chips. open drain: los1: r7 -- 0 ? , r96 -- 300 ? los2: r39 -- 0 ? , r97 -- 300 ? lol1: r8 -- 0 ? , r98 -- 300 ? lol2: r38 -- 0 ? , r99 -- 300 ? inttx1b: r92 C 10k ? , r42 -- 300 ? inttx2b: r94 C 10k ? , r46 -- 300 ? intrx1b: r93 C 10k ? , r43 -- 300 ? intrx2b: r95 C 10k ? , r47 -- 300 ? cmos: los1: r7 -- 300 ? , r96 C dnp los2: r39 -- 300 ? , r97 C dnp lol1: r8 -- 300 ? , r98 C dnp lol2: r38 -- 300 ? , r99 C dnp inttx1b: r92 C dnp, r42 -- 300 ? inttx2b: r94 C dnp, r46 -- 300 ? intrx1b: r93 C dnp, r43 -- 300 ? intrx2b: r95 C dnp, r47 -- 300 ? downloaded from: http:///
78P2352-DB demo board manual 5 pcb design description the 78P2352-DB (d2352t8 c ) demo board is constructed as a four-layer pc board. the top layer has the major components and signal routes. the bottom layer has bypass capacitors and mostly miscellaneous discrete components, as well as additional signal routes. the internal two layers have ground and power supply planes only. the power supply and ground pins of the 78p2352 liu are connected directly to these planes. the ground layer is directly under the component side of the board, followed by the power plane layer, then the bottom layer. ground the ground layer uses a split plane to divide system ground and frame (or chassis) ground. the frame ground plane is on the line side (the primary side of the transformer and the bncs) and system digital ground is the liu side (the secondary side of the transformer). the chassis plane typically will be connected to the equipment chassis, which connects to the facilities earth ground structure. the coax shield also typically connects to the chassis at equipment or patch panel bulkhead, providing a solid common bonding tie-point to the facilitys grounding structure, as specified in the itu-t recommendation k.27. tx- coax rx-coax liu frame ground component ground copper void vcc plane as with the digital ground plane, the power plane layer should only extends to the liu side of the transformer. the outer edge of the power plane is kept 10 mils short of the ground planes outer edge to avoid plane-to-plane current fringing at the plane edges. decoupling two decades of caps are used on the d2352t8 c demo board, e.g. a mix of 0.1uf and 0.001uf. consult the application note for general guidelines. analog traces all cmi transmitter and receiver differential pair signal routes have a differential impedance of 75 ? to the secondary side of the transformer. the line-side transmit pair (primary side of transformer), as well as the line side receive pair, is a 75 ? single-ended trace. the coax shield is connected directly to the line-side chassis ground. transformers the 78P2352-DB (d2352t8 c ) uses 1:1ct wide band transformers on transmit and receive. the following table lists the recommended transformers from different vendors that can be fitted on the 78P2352-DB demo board: dual core transformers manufacturer part number halo tg04-tdk1n1 tamura ttc-300 see application note for transformer specifications and other recommended vendors and part numbers. sample test results refer to appendix a for sample test results. schematics refer to appendix b for schematics and bill of material. test setup refer to appendix c for recommended test setups. downloaded from: http:///
78P2352-DB demo board manual 6 appendix a: sample test results mask measurments the following is a typical mask measurement for an stm-1e (cmi 0) pulse. figure a1 : stm-1e pulse mask (cmi 0) the following is a typical mask measurement for an stm-1e (cmi 1) pulse. figure a2 : stm-1e pulse mask (cmi 1) downloaded from: http:///
78P2352-DB demo board manual 7 jitter tolerance: the following are typical stm-1 jitter tolerance measurements when tested in remote loopback (see appendix c2). figure a3 : stm-1e jitter tolerance test result jitter transfer function: the following scope pics show the jitter transfer performance of the 78p2352. when tested in remote loopback (see appendix c2). figure a4 : stm-1e jitter transfer test result downloaded from: http:///
78P2352-DB demo board manual 8 appendix b: schematics & bill of material liu 78p2352 sdo cmio1p tx2ckp cmio2n sen tx2ckn pi22d pi21d ckrefp los2 sdi pi23d los1 eclo2n eclo1n tx1ckn sck pi10d eclo1p cmio1n pi1ck lpbk2 cmio2p pi11d porb pi20d tx1ckp pi2ck eclo2p lpbk1 si2ckp si2ckn si2dp si2dn so2ckp so2ckn so2dp so2dn so1dn so1dp so1ckn so1ckp si1dn si1dp si1ckn si1ckp pi13d pi12d po1ck po23d po20d po2ck po13d po22d po21d pto2ck po12d po11d pto1ck po10d cmii1p cmii1n cmii2p cmii2n ecli2p ecli2n ecli1p ecli1n spsl rcsl ckmode txpd d2352t8c 1 78p2352 customer demo board a 14 monday, april 26, 2004 tdk semiconductor corp. 6440 oak canyonirvine, ca 92618 714-508-8800 title size document number rev date: sheet of front endfront end cmio2n cmio2p cmio1p cmio1n cmii2n cmii2p ecli2p ecli1p ecli1n tx2ckn tx1ckn tx2ckp tx1ckp eclo1n eclo1p eclo2n eclo2p ecli2n cmii1p cmii1n digital interfacedigital side si2ckp si2ckn si1ckp si1ckn si1dp si1dn si2dp si2dn so2ckp so2ckn so2dp so2dn so1dn so1dp so1ckp so1ckn ckrefp sck sen sdi porb pi2ck pi20d pi21d pi22d pi23d pi13d pi12d pi11d pi10d pi1ck los1 los2 pto1ck po1ck po13d po12d po11d po10d pto2ck po2ck po23d po22d po21d po20d lpbk2 lpbk1 sdo rcsl ckmode spsl txpd downloaded from: http:///
78P2352-DB demo board manual 9 liu_sen c7 0.01uf 1 2 cmii1n vcc r31100 1 2 lpbk1 intrx@b d8 red led 1 2 so2dp pi20d vcc vcc lpbk1 lol1 r99300 r12 1k 1 2 sw1 sw dip-4 1 2 3 4 8 7 6 5 c20.1uf 1 2 si1dn pi10d 0 0 rsel2 1 2 3 r14 0 1 2 c50.1uf 1 2 ecli2p vcc spsl r42 300 1 2 ecli1n ser_sdi c240.1uf 1 2 vcc tx2ckn txpd lol1 r38 0 1 2 r43 300 1 2 ckrefp lpbk2 r7 0 1 2 cmio1n inttx!b r90 10k 1 2 po23d txout1 pdt14 1 2 r11 1k 1 2 po21d d4 red led 1 2 r10 1k 1 2 d5 red led 1 2 r35 0 1 2 ckmode c30.1uf 1 2 si2ckp vcc osc2 17.408mhz-20ppm 1 2 3 4 ena gnd o/p vcc r22 45 c10 0.01uf 1 2 sdo vcc so2ckn lpbk2 r15 0 1 2 r36 0 1 2 so1ckp pi2ck intrx!b lpbk1 r29 45 pi23d c230.1uf 1 2 ser_sdo intrx!b po10d c10.1uf 1 2 cmi r4010k 1 2 cmii1p par r4 0 1 2 r96300 d6 red led 1 2 cmio2n liu_sdi r13 0 1 2 sw2 sw-2 1 2 4 3 lpbk1 vcc r1 0 1 2 eclo1p sonet r9310k txpd r32 45 po1ck 0 0 rsel4 1 2 3 po22d liu_sen txpd r23 45 pi1ck cksl r87 49.9 sck jp3 sip3 1 2 3 r20 45 c13 0.001uf 1 2 lol2 r34 0 1 2 porb r24 45 r9410k so2ckp d7 red led 1 2 rcsl lol2 r39 0 1 2 so1ckn pi22d r5 10k 1 2 c12 0.001uf 1 2 inttx!b ckmode pi13d d2352t8c 1 78p2352 customer demo board b 24 monday, september 27, 2004 tdk semiconductor 6440 oak canyonirvine, ca 92618 714-508-8800 title size document number rev date: sheet of c860.1uf 1 2 pto1ck r30 45 pdt15 1 2 ext mon jp2 1 2 3 r46 300 1 2 r4110k 1 2 cmii2n r16 0 1 2 d1 red led 1 2 txout1 d2 red led 1 2 u1 tsc78p2352-exposed pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 129 txout1 txout0 nc nc vcc gnd si1ckp si1ckn inttx2b si1dp si1dn vcc gnd txpd ckmode rcsl lpbk1 lpbk2 los2 lol2 vcc gnd vcc gnd so1ckp so1ckn intrx2b so1dp so1dn pi1ck pi10d pi11d pi12d pi13d pto1ck gnd vcc po1ck gnd vcc po13d po12d gnd vcc po11d po10d gnd vcc vcc gnd po20d po21d vcc gnd po22d po23d vcc gnd po2ck vcc gnd pto2ck pi23d pi22d ecl1n ecl1p vcc tx1ckn tx1ckp gnd cmi1n cmi1p vcc rx1n rx1p gnd vcc vton vtop gnd gnd ckrefp ckrefn vcc gnd rx2p rx2n vcc cmi2p cmi2n gnd tx2ckp tx2ckn vcc ecl2p ecl2n sck_mon sen_cmi sdi_par sdo_e4 vcc gnd si2ckp si2ckn inttx1b si2dp si2dn vcc gnd porb gnd cksl los1 lol1 frst spsl nc2nc1 vcc gnd so2ckp so2ckn intrx1b so2dp so2dn pi2ck pi20d pi21d gnd tx2ckp open drain: los1: r7 - 0, r96 - 300 los2: r39 - 0, r97 - 300 lol1: r8 - 0, r98 - 300 lol2: r38 - 0, r99 - 300 inttx1b: r92 - 10k, r42 - 300 inttx2b: r94 - 10k, r46 - 300 intrx1b: r93 - 10k, r43 - 300 intrx2b: r95 - 10k, r47 - 300 d3 red led 1 2 los2 liu_sdo c200.1uf 1 2 r2 0 tx1ckn c210.1uf 1 2 c220.1uf 1 2 r18 45 spsl r26 45 si1ckp los1 liu_sck cmio1p r37 0 1 2 po13d r17 0 1 2 r21 45 pdt13 1 2 jp5 1 2 3 c60.1uf 1 2 si2ckn c8 0.01uf 1 2 vcc los1 sdi ser_sck inttx@b r97300 0 0 rsel1 1 2 3 r9510k loc r98300 so1dp so2dn jp6 1 2 3 eclo2p r6 33 1 2 pi12d po11d inttx@b cmos:los1: r7 - 300, r96 - dnp los2: r39 - 300, r97 - dnp lol1: r8 - 300, r98 - dnp lol2: r38 - 300, r99 - dnp inttx1b: r92 - dnp, r42 - 300 inttx2b: r94 - dnp, r46 - 300 intrx1b: r93 - dnp, r43 - 300 intrx2b: r95 - dnp, r47 - 300 r9 1k 1 2 c11 0.001uf 1 2 cmii2p vcc liu_sdi pdt17 1 2 los1 txout2lpbk2 e4 c170.1uf 1 2 osc1 19.44mhz-20ppm 1 2 3 4 ena gnd o/p vcc los1 ckmode liu_sck r47 300 1 2 eclo1n j1sma_top 2 3 5 4 1 ckmode frst tx1ckp los2 c160.1uf 1 2 tristate s1dip-8 tri state 8 7 6 5 4 3 2 1 9 10 po2ck jp8 header10 1 2 3 4 5 6 7 8 9 10 si1ckn vcc vcc r9210k ecli1p si2dn liu_sdo los2 0 0 rsel3 1 2 3 c40.1uf 1 2 ckrefp vcc los2 r19 100 1 2 r33 0 1 2 so1dn pi21d c180.1uf 1 2 pi11d c15 0.001uf 1 2 pdt16 1 2 si1dp intrx@b jp4 1 2 3 ecli2n vcc ser_sen po12d r27 45 txout2 c190.1uf 1 2 pdt18 1 2 si2dp rcsl spsl eclo2n lpbk2 r3 10k 1 2 r91 10k 1 2 rcsl e4 c9 0.01uf 1 2 cmio2p vcc vcc po20d vcc r28 45 jp7 1 2 3 c14 0.001uf 1 2 r78 300 1 2 pto2ck r80 1 2 jp1 1 2 3 c870.1uf 1 2 sen downloaded from: http:///
78P2352-DB demo board manual 10 c64 0.001uf 1 2 j12sma_top 2 3 5 4 1 c300.1uf 1 2 pi13d vcc po22d c320.1uf 1 2 si2dp g3 1 pi2ck lpbk1 c410.1uf 1 2 r56170 r51170 c400.1uf 1 2 r57170 g1 1 si1dn pdt2 tp 1 2 tp1 gnd so1dn pto2ck c370.1uf 1 2 j5sma_top 2 3 5 4 1 j3sma_top 2 3 5 4 1 po11d po2ck g5 1 c500.1uf 1 2 r85130 1 2 r7982 so2ckp c57 0.001uf 1 2 vcc j2sma_top 2 3 5 4 1 c260.1uf 1 2 pdt7 tp 1 2 c58 0.001uf 1 2 r8082 pi12d so2dn porb c390.1uf 1 2 po12d c59 0.001uf 1 2 r8182 c340.1uf 1 2 lpbk2 all decoupling capacitors should be placed onthe bottom of the board right under the chip. no two caps can be tied together through the same connection r52170 so1ckp r83130 1 2 c514.7uf g4 1 pdt5 tp 1 2 r8282 si1dp j4sma_top 2 3 5 4 1 so2dn po13d j7sma_top 2 3 5 4 1 pdt4 tp 1 2 c544.7uf j18bana-red 1 j17sma_top 2 3 5 4 1 pdt10 tp 1 2 pi22d pdt6 tp 1 2 j8sma_top 2 3 5 4 1 sdo c290.1uf 1 2 r54170 txpd c460.1uf 1 2 vcc j9sma_top 2 3 5 4 1 pi1ck vcc sck pi10d so2ckn los1 j15sma_top 2 3 5 4 1 spsl si1ckn j11sma_top 2 3 5 4 1 so2dp po1ck so2dp pi21d c53 0.01uf 1 2 j10sma_top 2 3 5 4 1 j6sma_top 2 3 5 4 1 sen r58 300 1 2 g2 1 c60 0.001uf 1 2 c310.1uf 1 2 c450.1uf 1 2 r45100 c270.1uf 1 2 los2 c63 0.001uf 1 2 c470.1uf 1 2 ckrefp pi11d pdt3 tp 1 2 pdt1 tp 1 2 c280.1uf 1 2 si2ckn vcc ckmode d2352t8c 1 78p2352 customer demo board b 34 monday, april 26, 2004 tdk semiconductor corp. 6440 oak canyonirvine, ca 92618 714-508-8800 title size document number rev date: sheet of vcc u2 amp-48-m-connector a1 c1 a3 a4 a5 a6 a7 b9 c3 b6 b7 b5 b8 b10 b4 b1 b2 b3 a11 a10 a15 a14 a12 a13 a2 c2 a8 a9 a16 b11 b12 b13 b14 b15 b16 c4 c5 c6 c7 c8 c9 c10 c12 c13 c14 c15 c16 c11 m1 m2 j19bana-black 1 so2ckn pi23d vcc c420.1uf 1 2 si1ckp po20d note: populate 0-ohm resistors onc29,c30,c31,c32 when connecting to the optical board. tp2 gnd sdi u3 ps-diode 3 2 1 4 i/o2 i/o1 gndvcc r50170 r86130 1 2 po21d c61 0.001uf 1 2 si2ckp r53170 pto1ck r55170 c250.1uf 1 2 c330.1uf 1 2 so1ckn si2dn g6 1 j16sma_top 2 3 5 4 1 pdt8 tp 1 2 c430.1uf 1 2 rcsl c55 0.001uf 1 2 j14sma_top 2 3 5 4 1 c52 0.01uf 1 2 c480.1uf 1 2 c350.1uf 1 2 r44100 c380.1uf 1 2 c62 0.001uf 1 2 c360.1uf 1 2 so2ckp pi20d c56 0.001uf 1 2 pdt9 tp 1 2 c490.1uf 1 2 c440.1uf 1 2 so1dp po10d j13sma_top 2 3 5 4 1 d9 green led 1 2 po23d r84130 1 2 downloaded from: http:///
78P2352-DB demo board manual 11 j22sma-top 2 3 5 4 1 r76 170 r65 100 1 2 c90dnp l1 3.3uh 1 2 tx1ckn r60170 c6810uf bnc1bnc_ra 1 2 3 4 5 c800.1uf 1 2 r1040 j21sma-top 2 3 5 4 1 c750.1uf 1 2 cmii2p c660.1uf 1 2 r64 170 eclo1p r68 170 1 2 c700.1uf 1 2 the frame gnd and digital groundshould be totally isolated and only the transformers should act as a bridge between the both grounds c7910uf vcc r1030 r7375 1 2 r1010 vcc r70 75 1 2 r69 170 vcc r1070 d14 bav99 3 1 2 cmii1p tp5 c85 0.001uf 1 2 d11 bav99 3 1 2 r75 170 tx2ckn c84 0.001uf 1 2 c730.1uf 1 2 r71 170 1 2 tp4 j23sma-top 2 3 5 4 1 vcc c650.1uf 1 2 t2 transformer dual ct 6 11 10 8 9 7 1 2 3 16 15 14 d13 bav99 3 1 2 r6675 1 2 cmii2n c88dnp eclo1n r62170 d17 bav99 3 1 2 bnc3bnc_ra 1 2 3 4 5 l4 3.3uh 1 2 c720.1uf 1 2 cmii1n r63170 c91dnp tx2ckp t1 transformer dual ct 3 14 15 1 16 2 8 7 6 9 10 11 ftcvr2 hfbr-5805b 1 2 3 4 5 6 7 8 9 10 11 veerx rdrd sd vccrx vcctx td td veetx m1 m2 l3 3.3uh 1 2 r74 100 1 2 cmio1n d15 bav99 3 1 2 ecli1n tp6 vcc r72 170 1 2 pdt11 tp 1 2 d12 bav99 3 1 2 r1000 connect frame to digitalground if needed ftcvr1 hfbr-5805b 1 2 3 4 5 6 7 8 9 10 11 veerx rd rd sd vccrx vcctx td tdveetx m1 m2 c810.1uf 1 2 c83 0.001uf 1 2 c6710uf d2352t8c 1 78p2352 customer demo board b 44 monday, april 26, 2004 tdk semiconductor corp. 6440 oak canyonirvine, ca 92618 714-508-8800 title size document number rev date: sheet of c740.1uf 1 2 r5975 1 2 pdt12 tp 1 2 c690.1uf 1 2 ecli2n frgnd cmio2n j20sma-top 2 3 5 4 1 cmio2p bnc4bnc_ra 1 2 3 4 5 vcc c710.1uf 1 2 c770.1uf 1 2 c7810uf r67 170 1 2 ecli1p cmio1p l2 3.3uh 1 2 r1060 r61170 r100-r107 are intended forimprove rl. values could be vary on different boards. d16 bav99 3 1 2 eclo2p tx1ckp bnc2bnc_ra 1 2 3 4 5 vcc r102 0 d10 bav99 3 1 2 ecli2p tp3 c89dnp c760.1uf 1 2 eclo2n c820.1uf 1 2 r1050 downloaded from: http:///
78P2352-DB demo board manual 12 bill of material item quantity reference part pcb footprint part number vendor 1 4 bnc1, bnc2, bnc3, bnc4 b nc_ra bnc_rt a24611-nd/413558-1 digikey amp 2 53 c1-c6, c16-c50, c65, c66, c69, c70, c71, c76, c77, c80, c81, c82, c86, c87 cap., 0.1uf, 16v c_0603 pcc2277ct-nd ecj-1vb1e104k c1608x7r1e104k digikey panasonic tdk 3 6 c7, c8, c9, c10, c52, c53 cap, 0.01uf, 50v c_0603 399-1091-1-nd c0603c103k5ractu c0603x5r0j103k digikey kemet tdk 4 18 c11, c12, c13, c14, c15, c55, c56, c57, c58, c59, c60, c61, c62, c63, c64, c83, c84, c85 cap, 0.001uf, 10v c_0603 pcc1772ct-nd ecj-1vb1h102k c1608x7r1h102k digikey panasonic tdk 5 2 c51, c54 cap, 4.7uf, 10v sacap 399-1587-1-nd t491a475k016as digikey kemet 6 4 c67, c68, c78, c79 10uf c_0805 not installed n/a 7 8 d1, d2, d3, d4, d5, d6, d7, d8 red led ledsmd 0805 l62411ct-nd cmd17-21src digikey chicago miniature lamp 8 1 d9 green led ledsmd 0805 l62505ct-nd cmd17-21vg digikey chicago miniature lamp 9 8 d10-d17 bav99 sot-23 bav99inct-nd bav99e6327 digikey infineon technologies 10 6 g1, g2, g3, g4, g5, g6 mthole mthole 1809k-nd h704-nd digikey 11 7 jp1, jp2, jp3, jp4, jp5, jp6, jp7 sip3 sip\3p s1011-03-nd pzc03saan digikey sullins electronics corp 12 1 j1 sma_top sma_top lti- sasf54gt lighthorse technologies 13 16 j2,j3,j4,j5,j6,j7,j8,j9,j10,j11,j12,j13,j14, j15,j16,j17,j20,j21,j22,j23 sma_edge sma_edge j502-nd 142-0701-801 digikey jonson components 14 1 j18 bana-red ban 16bj381 16bj381 mouser dgs pro-audio 15 1 j19 bana-black ban 16bj382 16bj382 mouser dgs pro-audio 16 16 pdt1,pdt2,pdt3,pdt4,pd t5,pdt6,pdt7,pdt8, pdt9,pdt10,pdt11,pdt12, pdt13,pdt14,pdt15,pdt16, pdt17,pdt18 tp sip\2p s1011-02-nd pzc02saan digikey sullins electronics corp downloaded from: http:///
78P2352-DB demo board manual 13 item quantity reference part pcb footprint part number vendor 17 4 rsel1,rsel2, rsel3,rsel4 res, 0, 5% rsel p0.0gct-nd erj-3gey0r00v digikey panasonic 18 17 r1,r2,r4,r7,r8,r13,r14,r15,r16,r17,r33, r34,r35,r36,r37,r38,r39 res, 0, 5% r_0603 p0.0gct-nd erj-3gey0r00v digikey panasonic 19 8 r3,r5,r90-95 res, 10k, 5% r_0603 p10kgct-nd erj-3geyj103v digikey panasonic 20 1 r6 res, 33, 5% r_0603 p33gct-nd erj-3geyj330v digikey panasonic 21 10 r42,r43,r46,r47,r58,r78, r96-r99 res, 300, 5% r_0603 p300gct-nd erj-3geyj301v digikey panasonic 22 4 r9,r10,r11,r12 res, 1k, 1% r_0603 p1.00khct-nd erj-eekf1001v digikey panasonic 23 12 r18,r20,r21,r22,r23,r24,r26,r 27,r28,r29,r30,r32 res, 43, 5% r_0603 p43gct-nd erj-3geyj430v digikey panasonic 24 6 r19,r31,r44,r45, r65,r74 res, 100, 1% r_0603 p100hct-nd erj-3ekf1000v digikey panasonic 25 2 r41,r40 res, 10k, 5% r_0805 p10kact-nd erj-6geyj103v digikey panasonic 26 16 r50,r51,r52,r53,r54,r55, r56,r57,r60,r61,r62,r63, r64,r67,r68,r69,r71,r72,r75,r76 res, 169, 1% r_0603 p169hct-nd erj-3ekf1690v digikey panasonic 27 4 r59,r66,r70,r73 res, 75, 1% r_0603 p75.0hct-nd erj-3ekf75r0v digikey panasonic 28 4 r83,r84,r85,r86 res, 130, 1% r_0603 p130hct-nd erj-3ekf1300v digikey panasonic 29 4 r79,r80,r81,r82 res, 82, 1% r_0603 311-82.0hct-nd 9c06031a82r0fkhft digikey yageo 30 1 r87 res, 49.9, 1% r_0603 p49.9hct-nd erj-3ekf49r9v digikey panasonic 31 1 sw1 sw dip-4 dip8 gh1004-nd 76sb04s digikey grayhill, inc. 32 1 sw2 sw-2 dip4 gh1002-nd 76sb02s digikey grayhill, inc 33 1 s1 dip-8 tri state dip8_tris 138991 eta-108e jameco ece 34 2 t1,t2 tg04-tdk1n1 dual ct tg04-tdk1n1 halo downloaded from: http:///
78P2352-DB demo board manual 14 item quantity reference part pcb footprint part number vendor 35 1 u1 78p2352 tqfp128 78p2352-igt teridian semiconductor 36 1 osc1 19.44mhz so4 asv-19. 44mhz-j abracon corporation 37 1 osc2 17.408mhz so4 asv-17. 408mhz-j abracon corporation 38 1 tp1/tp2 ground strip tp-025sq c2118b-100-nd/ c2118 digikey general cable 39 1 u3 diode sot-143 sr3.3 semtech 40 1 u2 amp-48 female connector amp-48r 650893-5-nd 650893-5 digikey amp downloaded from: http:///
78P2352-DB demo board manual 15 appendix c test measurement setups transmit pulse mask 78P2352-DB dut coax 3' scope tx rx stm1e / e4 cmi signal source coax amt 75 probe figure c1. notes: ? signal source (i.e. test equipment) transmits cmi coded data to the demo board. ? the demo board is configured in remote loopback mode. ? a 50 ? to 75 ? adaptor (i.e. tektronix amt 75) is needed for 50 ? scopes. tx test equipment coax tx rx coax 78P2352-DB dut jitter tolerance & transfer rx figure c2. notes: ? test equipment transmits cmi coded data to the demo board. ? the demo board is configured in remote loopback mode. ? run the receive jitter tolerance and/or jitter tr ansfer function (jtf) tests on the test equipment. downloaded from: http:///
78P2352-DB demo board manual 16 tx rx rx 78P2352-DB dut test equipment tx intrinsic (transmit) jitter coax stm1/e4 nrz signal source, no jitter figure c3. notes: ? nrz signal generator transmits data to the demo board via sma lvpecl inputs. ? the demo board is in thru-mode (no loopbacks). ? input signal should be free of jitter. this product is sold subject to the term s and conditions of sale supplied at the ti me of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. teridi an semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. tsc assumes no liability for applications assistance. teridian semiconductor corp., 6440 oak canyon, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com ? 2005 ? teridian semiconductor corporation 08/05 C rev 1.1 downloaded from: http:///

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